As is known in the art, analog-to-digital converters (ADCs) convert a signal in analog format to a signal in digital format. Conventional ADC circuits can have a variety of circuit architectures each of which has certain concomitant disadvantages. Known ADC architectures include pipeline, sigma-delta, cyclic, flash, successive approximation, and dual-slope. Each architecture is generally applicable to a limited operating range. That is, each of these architectures has strengths and weaknesses that make them more amenable to working in certain frequency and resolution ranges.
Some ADC architectures do not operate outside certain ranges or consume prohibitively high power in certain ranges as compared to other architectures. Even within preferred operating ranges, a given architecture can have a performance level that is dictated by certain circuit parameters that are fixed for a given design. For example, ADCs generally include op amps that operate at a speed dictated by the bandwidth required of them. To operate at different speeds, the op amp bandwidth must be altered in an efficient way. Likewise, the resolution of certain ADC architectures is fixed by the thermal noise contribution of the components within it and hence varies with the circuit design.
There have been various attempts to create digitization systems having a relatively wide operating range. One such method includes employing a single very high-performance ADC that can work at the highest common denominator of resolution and sampling rate. However, this strategy is not practical and is extremely power inefficient.
An alternate approach employs multiple A/D converter architectures each covering a small sector in the overall two-dimensional space. This implementation, however, requires a prohibitively large number of ADCs to achieve optimal power consumption with a reasonably fine granularity over input bandwidth and resolution. For example, the fraction of the application space bounded by data-rate and resolution ranging between 20 Hz–20 Khz and 8–18 bits, respectively; in order for the system to achieve a power consumption that in the worst case is as much as a factor four times the optimal level—would require the system to include 50 different converters working in tandem. This does not even consider a higher portion of the bandwidth spectrum. In a discrete chip implementation, there would be a tremendous power overhead merely due to vast amounts of PCB wiring to connect the various architectures.
U.S. Pat. No. 5,691,720 entitled “Delta sigma analog-to-digital converter having programmable resolution/bias current circuitry and method” provides variable resolution in a delta-sigma type ADC by controlling the Oversampling Ratio (OSR) of the ADC over certain fixed values. In order to make the opamps settle faster (because of the varying clock frequency), the bias current is varied over values that are predetermined for the each of the different oversampling ratios. This fixed arrangement offers relatively limited resolution reconfigurability at lower bandwidths. In addition, relying upon a predetermined bias current for each oversampling ratio works only if the relationship of speed of the operational amplifiers versus its bias current is fixed. However, this relationship does not hold over different fabrication processes. Even within the same process, it is not possible to know this relationship (especially since bias current variation would place the input devices of the opamps into different regimes) in advance of building the chip. While it is possible to make a calibration run for a given process and chip, this adds significant cost.
In another prior art attempt, Texas Instruments of Dallas Tex., manufactures an ADC having part number TLV1562. Currently, this ADC operates only at the following selected values: 10 bit/3 Msps, 8 bit/4 Msps and 4 bit/8 Msps. Thus, this ADC offers limited reconfigurability.
U.S. Pat. No.5,877,720 entitled “Reconfigurable analog-to-digital converter” discloses a flash ADC having a limited reconfigurability, i.e., 2 settings: 5.75 b 350 Msample/s or 6.75 b 150 Msample/s.
Yet another approach is described in “A CMOS Programmable Self-Calibrating 13-bit Eight Channel Data Acquisition Peripheral,” Ohara et. al., Journal of Solid-State Circuits, December, 1989. This article describes an ADC having resolution reconfigurability with a single cyclic ADC that can be configured for 8, 13, or 16 cycles. It should be noted that this architecture can work at 16 bits only with elaborate digital calibration.
It would, therefore, be desirable to provide a reconfigurable ADC that overcomes the aforesaid and other disadvantages.